JPS59133738A - Pllシンセサイザ方式 - Google Patents

Pllシンセサイザ方式

Info

Publication number
JPS59133738A
JPS59133738A JP58007570A JP757083A JPS59133738A JP S59133738 A JPS59133738 A JP S59133738A JP 58007570 A JP58007570 A JP 58007570A JP 757083 A JP757083 A JP 757083A JP S59133738 A JPS59133738 A JP S59133738A
Authority
JP
Japan
Prior art keywords
frequency
vco1
voltage
circuit
control voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58007570A
Other languages
English (en)
Japanese (ja)
Other versions
JPH055207B2 (en]
Inventor
Shiro Fujiki
藤木 詩郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaesu Musen Co Ltd
Original Assignee
Yaesu Musen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaesu Musen Co Ltd filed Critical Yaesu Musen Co Ltd
Priority to JP58007570A priority Critical patent/JPS59133738A/ja
Publication of JPS59133738A publication Critical patent/JPS59133738A/ja
Publication of JPH055207B2 publication Critical patent/JPH055207B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0805Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/187Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)
JP58007570A 1983-01-20 1983-01-20 Pllシンセサイザ方式 Granted JPS59133738A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58007570A JPS59133738A (ja) 1983-01-20 1983-01-20 Pllシンセサイザ方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58007570A JPS59133738A (ja) 1983-01-20 1983-01-20 Pllシンセサイザ方式

Publications (2)

Publication Number Publication Date
JPS59133738A true JPS59133738A (ja) 1984-08-01
JPH055207B2 JPH055207B2 (en]) 1993-01-21

Family

ID=11669464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58007570A Granted JPS59133738A (ja) 1983-01-20 1983-01-20 Pllシンセサイザ方式

Country Status (1)

Country Link
JP (1) JPS59133738A (en])

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2344006A (en) * 1998-11-23 2000-05-24 Motorola Inc Direct modulation phase lock loop and method therefor
JP2003505901A (ja) * 1999-07-19 2003-02-12 ケンブリッジ シリコン ラジオ リミテッド 調整可能なフィルタ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676639A (en) * 1979-11-27 1981-06-24 Trio Kenwood Corp Synthesizer receiver

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676639A (en) * 1979-11-27 1981-06-24 Trio Kenwood Corp Synthesizer receiver

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2344006A (en) * 1998-11-23 2000-05-24 Motorola Inc Direct modulation phase lock loop and method therefor
GB2344006B (en) * 1998-11-23 2001-01-17 Motorola Inc Phase lock loop and method therefor
JP2003505901A (ja) * 1999-07-19 2003-02-12 ケンブリッジ シリコン ラジオ リミテッド 調整可能なフィルタ

Also Published As

Publication number Publication date
JPH055207B2 (en]) 1993-01-21

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